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Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic levels & high impedance state is electrical open circuit conditions. Tri-state logic has a third line known as enable line.
Design goals: The correct form of a computer system depends on the constraints and aim for which it was optimized. Computer architectures frequently trade off cost, standard
Representation scheme in artificial intelligence: It is not hard to see why logic has been popular representation scheme in AI: In this way, It is easy to represent knowl
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Define Mapping and List mapping procedure? The transformation of data from main memory to cache memory is known as an Mapping. Associative mapping Direct mapping
Explain Sequential logic circuit Ans. Sequential logic circuit:- (i) Output not only depends upon the recent state of the input but also depend upon the earlier state
What is memory mapped I/O? When the I/O devices share the similar address space, the arrangement is known as memory mapped I/O.
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Explain SR Latch with NAND Gate? SR Latch has two useful states: Set state, when output Q=1 and Q'=0. Reset state, when output Q=0 and Q'=1.Output Qand Q' are normally
What is a digital comparator? Ans: Digital Comparator: The comparison of two numbers is an operation which evaluates if one number is greater than, less than, or equival
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