What is the difference between wire and reg

Wire

Wire is used for designing combinational logic, as we all know that this type of logic cannot store a value.  As  you  can  see  from  the  illustration above,  a  wire  can  be  assigned  a  value  by  an  assign statement. Default data type is wire: this means that if you declare a variable without specifying reg or wire, it would be a 1-bit wide wire.

module wire_example( a, b, y);

input a, b;

output y;

wire a, b, y;

assign y = a & b;

endmodule

Register

Reg can store value and drive strength. Something which we need to know about reg is that it can be used for modeling both sequential and combinational logic. Reg data type can be driven from initial and always block.