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What is Race-around problem? How can you rectify this?
The clock pulse which remains into the 1 state whereas both J and K are equal to 1 will reason the output to complement again and repeat complementing till the pulse goes back to 0, which is termed as the race around problem. To ignore this undesirable operation, the clock pulse should have a time duration which is shorter than the propagation delay time of the F-F, which is restrictive therefore the alternative is master-slave or edge-triggered construction.
In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why? Yes in a pure combinational circuit is it essential to mention all
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