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What is horizontal and vertical parity
A single error can cause both horizontal and vertical parity checks to be wrong. Two errors can also be easily detected. If they are not in similar rows, row parity will catch them. If they are in same row, column parity will catch them. Three errors might slip by undetected, such as, if some bit is inverted along with its column and row parity bits. Even corner bit will not catch this.
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What is the implication of increasing and decreasing subnet Bits?
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