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What are parity generator and checker?
Ans:
While a digital signal is transmitted, this may not be received correctly through the receiver. At the receiving end this may or may be impossible to detect the error. To overcome this difficulty, an extra bit is attached to the n-bit code word to create the number of bits (n+1) in that a way in order to make the number of ones in the resulting (n+1) bit code odd or even. After that this will be an error detecting code. Therefore for detection of error this extra bit is termed as parity bit. Parity term is utilized to specify the number of ones in a word like odd or even. A logic circuit which checks the parity of a binary word is termed as parity checker. Likewise a logic circuit which generates an additional bit to make the digital word of required parity (even or odd) is called parity generator.
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a) Prototype a macro known AP which takes 4 integer parameters n (number of terms), a (first term), l (last term) and Sum (sum of n terms), provided that: Sum = (a+l)*n/2 b)
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