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A data set with 1000 rows is input to a neural network in Weka. The test option is set to 10-fold cross validation and the neural network option validationSetSize = 20%. How many rows of data are used in a validation set in a fold?
A support vector machine in Weka uses a Gaussian (radial basis function) kernel with parameter gamma. Gamma should be selected less than or equal to one. Circle True or False.
A support vector machine in Weka uses a Gaussian (radial basis function) kernel with parameter gamma = 0.2. This corresponds to the parameter σ2 equal to what value?
A full adder logic circuit will have ? Ans. The full adder logic circuit also accounts the carry i/p generated in the earlier stage and it will add two bits. Hence three inputs
For what an append query be used? It is simple to append records from one table to another using an append query. There is no requirement for the tables to have the similar num
Explain the importance of Computer architecture Computer architecture courses cover application, organization, architecture, logic and transistor layers. However, four other la
How do you create special files like named pipes and device files? The system call method forms special files in the following sequence. Kernel assigns new inode,
Q. Explain Open-systems interconnections architecture model The most common network architecture model is the open-systems interconnections (OSI). Figure shows the ISO (Intern
Explain difference between Dynamic and static binding. Dynamic and static binding: Dynamic binding is a binding performed after the execution of a program has immediately beg
Inherent addressing Here the address is already built in to the instruction i.e. inherent to the code ABA ; Add A to B and store the answer in A Simple programs using
projections
Q. Describe buffer of receiving process? MPI_Gather (Sendaddr, Scount, Sdatatype, Receiveaddr, Rcount, Rdatatype,Rank, Comm): 'Using this function process with rank' rank
What is MMU? MMU is the Memory Management Unit. It is a special memory control circuit used for executing the mapping of the virtual address space onto the physical memory.
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