State the datatypes of Verilog

Verilog. Compared to VHDL, Verilog data types are very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by Verilog language and not by the user. There are net data types, for instance wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in implied modeled circuit.

Objects, that is signals, of type reg hold their value over simulation delta cycles and must not be confused  with  modeling  of  a  hardware  register.  Verilog  may  be  preferred  due to it's simplicity.