Software architecture of microprocessor, Computer Engineering

Assignment Help:

The 68HC11 series is based on the Motorola 6800/1 programming instruction set and hence is a fairly simple 8 bit microprocessor. The internal structure of the 6800/1 is shown below

The 6800/1 contains two 8 bit accumulators namely A,B which are used to process/hold data for the Arithmetic/Logic calculations . These can be combined to form one single 16 bit accumulator namely D. Also included are two 16 bits index register IX, IY which are mainly used for  pointing too addresses , but can also be used as a 16 bit store or counter. The next two 16 bits registers are the Program counter (PC) used for holding the current address of the program and the stack pointer (SP) used for holding the address of the next available stack (RAM) position .The final register is a 8 bit register called the condition code register (CCR) , this is used to hold the results of the last ALU operation , each bit (flag) is a particular ALU condition  as shown below

2029_Software Architecture of microprocessor.png

C- Carry/Borrow flag if set indicates that an arithmetic carry/borrow has occurred

V overflow if set indicates that the answer was greater that 8 bits  

Z zero flag if set if the ALU answer has produced a zero  

N - Negative if set this indicates that a negative number has been generated i.e. bit 7 = 1  

I - Interrupt mask if set stops further masked interrupts from happening

H Half carry, if set indicates that a half carry has occurred i.e. ALU result has caused a carry to occur between bit 3,4

X - Interrupt mask, if set indicates that a non masked interrupt has occurred i.e. Reset or XIRQ. Cleared by TAP or RTI

S Stop disable if set disables the use of the stop instruction, if cleared enables the stop command

The 68HC11 instruction set consists of three major groups:
 
          Maths Functions 
          Movement functions
          Processor commands
 
Before we tackle each section we shall first discuss the various addressing modes of each instruction


Related Discussions:- Software architecture of microprocessor

Determine the quivalence partitioning, Determine the quivalence Partitionin...

Determine the quivalence Partitioning? The division of domain data into dissimilar equivalence data classes is performed using Equivalence Partitioning. It is executed for redu

Explain difference between space and time division switching, Through two b...

Through two block diagrams explain the difference between Space division and time division switching. Space and Time Switching: Space Switches: Connections can be made i

Translation look aside buffer - computer architecture, Translation Look asi...

Translation Look aside Buffer :    A TLB is a cache that holds only page table mapping If there is no matching entry in the TLB for a page ,the page table have to

What is a client in sap terminology, What is a client in SAP terminology? ...

What is a client in SAP terminology? A S/W component that uses the service (offered by a s/w component) is known as a Client.  At the similar time these clients may also be ser

What is the function of a data element, What is the function of a data elem...

What is the function of a data element? A data element defines the role played by a domain in a technical context.  A data element having of semantic information.

Show sample instruction format of mips instruction, Q. Show Sample Instruct...

Q. Show Sample Instruction Format of MIPS instruction? Early MIPS architectures had 32-bit instructions and later versions have 64-bit implementations. The first commercial

What is insertion point, A vertical flashing line that permits the user whe...

A vertical flashing line that permits the user where text will be inserted.

Depth - basic characteristics of an experts system, An expert system has d...

An expert system has death that is it operate effectively in a narrow domain containing difficult challenging problems. Thus the rules in an experts systems are necessarily co

What is mini frame size where propagation speed is 200 m µs, A CSMA/CD bus ...

A CSMA/CD bus spans a distance of 1.5 Km. If data is 5 Mbps, What is minimum frame size where propagation speed in LAN cable is 200 m µs. Usual propagation speed in LAN cables

What is graceful degradation, What is graceful degradation? In multipro...

What is graceful degradation? In multiprocessor systems, failure of one processor will not halt the system, but only slow it down by sharing the work of failure system by other

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd