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What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
When there are multiple nonblocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example
always @ (posedge clk) begin
out <= in1^in2;
out <= in1 &in2;
out <= in1|in2;
In the instance just shown, it's the OR logic that is the last assignment. Hence, logic synthesized was indeed the OR gate. Had the last assignment been the "&" operator, it would have synthesized an AND gate.
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