Physical Memory Mapped I/O and Port I/O :

CPU controlled I/O comes in 2 ways. Simply the difference is whether we utilize the normal memory addresses for I/O, this is mention to as physical memory mapped I/O, or whether we set up a completely separate section of memory addresses which may ONLY be used for I/O, called port or I/O mapped I/O and addressed I/O Thus the latter has 2 separate addressing areas for the CPU, one for normal (physical) memory, one for I/O, while the former has only one which serves both purposes.The other difference between these 2techniques is that with memory mapped I/O the similar processor instructions that are utilized for transferring data to and from the processor registers and memory, or for testing the content of a memory register and so on, are utilized for the I/O operation, whereas port-addressed I/O has particular instructions (load and store) which may only be used for I/O operations, and have different codes and mnemonics.  In  the case  data  might always  be  transferred  into  a  processor  register, and in the  latter instructions like SUB,ADD (subtract) and CMP (compare) can refer to the input/output registers.

The peripheral controller serves to put the data at the proper memory locations, memory mapped or port addressed as can be. It will also provide control registers to determine whether data can be inputted or outputted, that is whether the external connections are for input or output of data, since they are often shared. The processor cannot read and write at the same location, it must do 1 or the other.

Also there will be a 'status' register which contain various 'flags' which signal to the processor that some of data has been placed for reading. Some of these can also be observable as connections to the outside world, to show, for instance, that the processor has supplied data for output. The registers are the similar size as the computer memory locations, generally 8-bit,-byte sized, so that they generally occupy 1 memory address each. The real number of addresses depends on the complication and functions provided by the peripheral controller