Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Consider the hardware design as shown. Within the target system the EPROM would contain the hex data as shown below
Address Assembly code 8000 86 8001 fe 8002 8b 8003 01 . ......... FFFE 80 FFFF 00 On power on the microprocessor issues a reset which causes the processor to go into an interrupt mode, because the interrupt is a reset, the microprocessor reads the two top bytes from memory i.e fffe and ffff. These are called the initial program counter RESET vectors. In this case the processor would then load in the 16 bit address 8000 and load this directly into the program counter (PC). This causes the processor to jump to address 8000 and start the actual program. The processor then reads the next byte from address 8000; this is 86 Hex and translates it to a load A instruction with immediate data where the data follows in the next byte. The PC is incremented by 1 i.e 8001 and fe in read in . This takes two cycles and termed the 'Fetch cycle'. The next stage is the microprocessor to perform the instruction i.e. transfer the data fe into A, this is termed the 'Execution cycle'. The whole cycle starts again, i.e. the PC is incremented to 8002 and the command 8b (ADDA) is fetched and interpreted as a ADDA, the PC in incremented to 8003 and the data is read in i.e. 1. The command is then executed and the next instruction read in at 8004 and so on. A day in the life of the micro controller is one of fetching and executing. The initial data in the EPROM at address fffe, ffff is termed the reset vector and is an reserved area of memory for the programmers (us) to place vector address i.e. start address of programs to deal with exceptions i.e. Clock Fail, IRQ, Timer output, Serial communications etc.
The full vector table is shown .Although we have not actually used the stack, the emulator which we use to debug hardware/software programs uses a small part of it , therefore it is important that we initialise the stack , therefore the full program for adding two numbers is shown below
Name add P6811 org $8000 ; Start address of program main: Lds #$1ff ; Set SP to top of internal Ram Ldaa #$fe adda #$1 loop0: jmp loop0 ; loop forever org $fffe FDB main ;Reset vectors END The bold sections are termed assembler directives and are used to control the assembler; the simplest ones are ORG which stands for origin, i.e. start code at this address , the P6811 indicates 68HC11 processor and END which tells the assembler to stop. FDB informs the assembler to insert a double byte i.e. 16 bits of the address labelled main i.e. 8000.
Mathematical Simulation and Modeling Applications The tasks including modeling and mathematical simulation require a lot of parallel processing. Three basic formalisms in model
What is semaphores? A semaphore 'S' is a synchronization tool which is an integer value that, apart from initialization, is accessed only by two standard atomic operations; wa
Q. Describe Message Passing Model? In message-passing model there be a set of tasks which employ their own local memories at the time of computation. Many tasks may inhabit on
what is spatial parallelis
When an input signal A=11001 is applied to a NOT gate serially, its output signal is ? Ans. First input applied will be LSB 00110, as A=11001 is serially applied to a NOT gate
Q. Make a generalized program that accepts a number & base, convert it into the given base. Perform necessary validations.
Question 1 Explain briefly the process of matching production rules against working memory 2 Explain Simplification, Conjunction and Transportation in propositional logic by
Give example of bus and memory transfer For example, the read operation for transfer of a memory unit M from address register AR to another data register DR can be illustrated
where do i get some sample assembly projects (with coding included)?
Given: • A sequence of n arrival times t0, t1, ..., tn-1, • a library of mlogically equivalent gates {(d0, c0), (d1, c1), ..., (dm-1,cm-1)} where d is delay and c is cost • a
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd