Multiple assign statements targeting the same wire, Computer Engineering

Assignment Help:

What logic is inferred when there are multiple assign statements targeting the same wire?

It's illegal to specify multiple assign statements to the same wire in a synthesizable code that will become  an  output  port  of  module.  Synthesis  tools  give  a  syntax  error  that  a  net  is  being driven by more than one source.

Illegal Code

Wire temp;

Assign temp = in1 & in2;

Assign temp = in3 & in4;

However, it is legal to drive a three-state wire by multiple assign statements.

Legal code

Wire temp;

Assign temp = enable1? (In1 & in2): 1'bz;

Assign temp = enable2? (In3 & in4): 1'bz

 


Related Discussions:- Multiple assign statements targeting the same wire

Link your documents to site, Images in the top area of Compass home page gu...

Images in the top area of Compass home page guide visitors to specific pages on the site. Now you will add links for navigation buttons. You will see that there are some ways to

Explain host function, Explain Host function Host function: accepts nam...

Explain Host function Host function: accepts name of floating-point guest function with single floating-point argument as its first argument, evaluates this function at x (the

Design combinational-sequential electronic logic gate, Combinational/Sequen...

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package) Car wash concept with the following steps in a Combinational Logic Diagram: 1.    Start

Mpi communications, We have to use 3 MPI communications: Plz the code in C+...

We have to use 3 MPI communications: Plz the code in C++     1.  MPI_Scatter 2.  MPI_Alltoall 3.  MPI_Gather     **The length of the array will be determined by the user Fir

What is usb, What is USB USB (UNIVERSAL SERIAL BUS) is intended to conn...

What is USB USB (UNIVERSAL SERIAL BUS) is intended to connect peripheral devices like mouse, keyboards, modems and sound cards to microprocessor through a serial data path and

Internrt application, what is the significance of telecommunications deregu...

what is the significance of telecommunications deregulation for managers and organization

Over fitting considerations, Over fitting Considerations : Hence in le...

Over fitting Considerations : Hence in left unchecked there backpropagation in multi-layer networks can be highly susceptible to overfitting itself to the training examples. B

Explain optimization process of pipelining, Q. Explain Optimization process...

Q. Explain Optimization process of Pipelining ? RISC machines can use a very efficient pipeline scheme due to the regular and simple instructions. Similarly all other instructi

Error detection mechanism must be in-built, Error detection mechanism may i...

Error detection mechanism may include checking mechanical and data communication errors. These errors must be reported to processor. The illustrations of kind of mechanical errors

Fully parallel associative processor (fpap), Fully Parallel Associative Pro...

Fully Parallel Associative Processor (FPAP):  This processor accepts the bit parallel memory organisation. FPAP has two type of this associative processor named as: Word Org

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd