What logic is inferred when there are multiple assign statements targeting the same wire?

It's illegal to specify multiple assign statements to the same wire in a synthesizable code that will become  an  output  port  of  module.  Synthesis  tools  give  a  syntax  error  that  a  net  is  being driven by more than one source.

Illegal Code

Wire temp;

Assign temp = in1 & in2;

Assign temp = in3 & in4;

However, it is legal to drive a three-state wire by multiple assign statements.

Legal code

Wire temp;

Assign temp = enable1? (In1 & in2): 1'bz;

Assign temp = enable2? (In3 & in4): 1'bz