Methods for organising the associative memory, Computer Engineering

Assignment Help:

There are two methods for organising the associative memory based on bit slices:

Bit parallel organisation:In this organisation every bit slices which are not masked off, participate in the comparison process, i.e., every words are used in parallel.

Bit Serial Organisation: In this organisation, only single bit slice participate in the operation across all the words. The bit slice is selected through a control unit and extra logic. This organisation is slower in speed but needs lesser hardware as compared to bit parallel which is much faster.

Related Discussions:- Methods for organising the associative memory

Learning abilities of perceptrons - ann, Learning Abilities of Perceptrons ...

Learning Abilities of Perceptrons - Artificial intelligence Computational learning theory is the study of what concepts specific learning schemes (representation and method) ca

What is ''LRU'' page replacement policy, 'LRU' page replacement policy is ?...

'LRU' page replacement policy is ? Ans. Least Recently Used.

Why 256 x 8 memory chips is require to design 2k x 8 memory, A number of 25...

A number of 256 x 8 bit memory chips are available. To design a memory organization of 2 K x 8 memory. Identify the requirements of 256 x 8 memory chips and explain the details.

#Information security, Imp questions solution

Imp questions solution

Advantage of wrapping database calls into mts transactions, Advantage of wr...

Advantage of wrapping database calls into MTS transaction If database calls are complete within the context of a transaction, aborting the transaction will undo and changes that

Search in problem solving - artificial intelligence, Search in Problem Sol...

Search in Problem Solving: If Artificial Intelligence can inform that the other science about anything, it is about problem solving and, in particular, how to research after s

Define flash memory, Define Flash Memory. It is an approach same to EEP...

Define Flash Memory. It is an approach same to EEPROM technology. A flash cell is based on a one transistor controlled by trapped charge just like an EEPROM cell.

Different ways in which a thread can be cancelled, What are the different w...

What are the different ways in which a thread can be cancelled? Cancellation of a target thread may occur in two different scenarios: Asynchronous cancellation: One thre

large block , Given a RAID 3 (bit-interleaved parity) with k disks, how we...

Given a RAID 3 (bit-interleaved parity) with k disks, how well will large block transmits work? How well will it handle a high I/O request rate? Compare the performance to a one di

Define bcd, Define BCD. A binary code that distinguishes between 10 ele...

Define BCD. A binary code that distinguishes between 10 elements must contain at least 4 bits, but 6 combinations will remain unassigned. Numerous dissimilar codes can be obtai

Write Your Message!

Name

Email id

Message

Verfication Code

User Account

All Pages