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Interfaced 2k X 8 (i.e 2716) EPROM using multiple input NAND gate decoder for memory locations FF800H-FFFFFH.
Simple NAND gate Decoder: While the 2k x 8 EPROM is used so address connection A10 to A0 of the 8088 are connected to address inputs A10 to A0 of the EPROM. The last nine address pins (A19 to A11) are connected to the inputs of a NAND gate decoder. This decoder selects the EPROM by one of the a few 2Kbyte sections of the whole 1Mbyte address range of the 8088 microprocessor.
A simple NAND gate decoder used to select a 2716 EPROM
Within this circuit, a single NAND gate decodes the memory address. This output of the NAND gate is logic 0 when the 8088 address pins connected to its inputs (A19 to A11) are all logic 1s. This active low, logic 0 output of the NAND gate decoder is attached to the CE' input pin which selects (enables) the EPROM.
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