Intel architecture – 64, Computer Engineering

Assignment Help:

IA-64 (Intel Architecture-64) is a 64-bit processor architecture created in cooperation by Hewlett-Packard and Intel applied by processors like Itanium. The objective of Itanium was to create a 'post-RISC era' architecture employing EPIC (Explicitly Parallel Instruction Computing).

1 EPIC Architecture

In this system a complex decoder system inspects every instruction as it flows by pipeline and sees that which is able to be fed off to function in parallel across available execution units for example a series of instructions for executing computations.

 A = B + C and

 D = F + G

These would be independent of one another and won't affect one another and so they can be fed in 2 numerous execution units and run in parallel. The capability to extract instruction level parallelism (ILP) from instruction stream is necessary for high-quality performance in a modern CPU.

Forecasting which code can and which cannot be divide up this way is a exceptionally complicated task. In many cases inputs to one line are dependent on output from another however only if some other condition is true. For illustration Think about slight modification of illustration noted before A = B + C IF A==5 THEN D = F + G. In this case calculations stay independent of other however second command needs results from first calculation in order to know if it must be run at all.

In these cases circuitry on CPU generally 'guesses' what condition will be. In something such as 90% of all cases an IF would be taken suggesting that in our illustration second half of command can be safely fed in another core. But getting guess wrong can cause a important performance hit when result has to be thrown out in addition CPU waits for results of 'right' command to be computed. Much of improving performance of modern CPUs is because of better prediction logic however recently improvements have begun to slow. Branch prediction accurateness has reached figures in excess of 98% in recent Intel architectures and raising this figure can only be attained by devoting more CPU die space to branch predictor a self-defeating tactic since it will make CPU more costly to manufacture.

IA-64 instead depends on compiler for this task. Even before program is fed in CPU compiler inspects code and makes same sorts of decisions which would otherwise happen at 'run time' on chip itself. Once it has determined what paths to take it collects up instructions it knows can be run in parallel and bundles them in one larger instruction and then stores it in that form in program.


Related Discussions:- Intel architecture – 64

What is an orthogonal base class in c++, If two base classes have no overla...

If two base classes have no overlapping methods or data they are said to be independent of, or orthogonal to each other. Orthogonal in the sense means that two classes function in

Instruction cycle-flynn’s classification, Instruction Cycle The instruc...

Instruction Cycle The instruction cycle consists of a series of steps needed for the implementation of an instruction in a program. A typical instruction in a program is descri

How a file can be shared among different users, Discuss the different techn...

Discuss the different techniques with which a file can be shared among different users. Several popular techniques with that a file can be shared among various users are: 1

Multiple assign statements targeting the same wire, What logic is inferred ...

What logic is inferred when there are multiple assign statements targeting the same wire? It's illegal to specify multiple assign statements to the same wire in a synthesizable

Differentiate between static and dynamic step loops, Differentiate between ...

Differentiate between static and dynamic step loops. Step loops fall into two classes: Static and Dynamic.  Static step loops have a fixed size that cannot be changed at runti

Explain lan topologies, Explain LAN Topologies and its basic topologies. ...

Explain LAN Topologies and its basic topologies. LAN Topologies: Network topology is a physical schematic that shows interconnection of the various users. There are four fund

Full form of www, What do you understand by WWW WWW: The World Wide ...

What do you understand by WWW WWW: The World Wide is an architectural framework for accessing linked documents increase out over thousands of machines all over the world. It

Show types under which networks will be divided, What are the two broad typ...

What are the two broad types under which Networks will be divided? Ans: All computer networks fit in one of the two dimensions specifically: a)  Transmission Technology, thi

How do you perform functional testing under load, Functionality under load ...

Functionality under load can be tested by running various Vusers concurrently. By enhancing the amount of Vusers, we can verify how much load the server can sustain.

Define memory address map, Define memory address map? Addressing of mem...

Define memory address map? Addressing of memory can be established by means of a table that specifies the memory address assigned to each chip. The tables, known as memory addr

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd