IA-64 (Intel Architecture-64) is a 64-bit processor architecture created in cooperation by Hewlett-Packard and Intel applied by processors like Itanium. The objective of Itanium was to create a 'post-RISC era' architecture employing EPIC (Explicitly Parallel Instruction Computing).

1 EPIC Architecture

In this system a complex decoder system inspects every instruction as it flows by pipeline and sees that which is able to be fed off to function in parallel across available execution units for example a series of instructions for executing computations.

 A = B + C and

 D = F + G

These would be independent of one another and won't affect one another and so they can be fed in 2 numerous execution units and run in parallel. The capability to extract instruction level parallelism (ILP) from instruction stream is necessary for high-quality performance in a modern CPU.

Forecasting which code can and which cannot be divide up this way is a exceptionally complicated task. In many cases inputs to one line are dependent on output from another however only if some other condition is true. For illustration Think about slight modification of illustration noted before A = B + C IF A==5 THEN D = F + G. In this case calculations stay independent of other however second command needs results from first calculation in order to know if it must be run at all.

In these cases circuitry on CPU generally 'guesses' what condition will be. In something such as 90% of all cases an IF would be taken suggesting that in our illustration second half of command can be safely fed in another core. But getting guess wrong can cause a important performance hit when result has to be thrown out in addition CPU waits for results of 'right' command to be computed. Much of improving performance of modern CPUs is because of better prediction logic however recently improvements have begun to slow. Branch prediction accurateness has reached figures in excess of 98% in recent Intel architectures and raising this figure can only be attained by devoting more CPU die space to branch predictor a self-defeating tactic since it will make CPU more costly to manufacture.

IA-64 instead depends on compiler for this task. Even before program is fed in CPU compiler inspects code and makes same sorts of decisions which would otherwise happen at 'run time' on chip itself. Once it has determined what paths to take it collects up instructions it knows can be run in parallel and bundles them in one larger instruction and then stores it in that form in program.