Intel architecture – 64, Computer Engineering

Assignment Help:

IA-64 (Intel Architecture-64) is a 64-bit processor architecture created in cooperation by Hewlett-Packard and Intel applied by processors like Itanium. The objective of Itanium was to create a 'post-RISC era' architecture employing EPIC (Explicitly Parallel Instruction Computing).

1 EPIC Architecture

In this system a complex decoder system inspects every instruction as it flows by pipeline and sees that which is able to be fed off to function in parallel across available execution units for example a series of instructions for executing computations.

 A = B + C and

 D = F + G

These would be independent of one another and won't affect one another and so they can be fed in 2 numerous execution units and run in parallel. The capability to extract instruction level parallelism (ILP) from instruction stream is necessary for high-quality performance in a modern CPU.

Forecasting which code can and which cannot be divide up this way is a exceptionally complicated task. In many cases inputs to one line are dependent on output from another however only if some other condition is true. For illustration Think about slight modification of illustration noted before A = B + C IF A==5 THEN D = F + G. In this case calculations stay independent of other however second command needs results from first calculation in order to know if it must be run at all.

In these cases circuitry on CPU generally 'guesses' what condition will be. In something such as 90% of all cases an IF would be taken suggesting that in our illustration second half of command can be safely fed in another core. But getting guess wrong can cause a important performance hit when result has to be thrown out in addition CPU waits for results of 'right' command to be computed. Much of improving performance of modern CPUs is because of better prediction logic however recently improvements have begun to slow. Branch prediction accurateness has reached figures in excess of 98% in recent Intel architectures and raising this figure can only be attained by devoting more CPU die space to branch predictor a self-defeating tactic since it will make CPU more costly to manufacture.

IA-64 instead depends on compiler for this task. Even before program is fed in CPU compiler inspects code and makes same sorts of decisions which would otherwise happen at 'run time' on chip itself. Once it has determined what paths to take it collects up instructions it knows can be run in parallel and bundles them in one larger instruction and then stores it in that form in program.


Related Discussions:- Intel architecture – 64

Explain the term - rational rose and visio 2000 enterprise, Explain the ter...

Explain the term - Rational Rose and Visio 2000 Enterprise Rational Rose: IBM Rational RequisitePro is a powerful and easy-to-use tool for use case management and requirement

Eme, state function and path function

state function and path function

System engineering hierarcy, develop system engineering hirarcy for public ...

develop system engineering hirarcy for public health care?

Work systems framework - information system, The Work Systems Framework - I...

The Work Systems Framework - Information System Adler writing in 1992 used the phrase 'stumbling backwards into the future' to describe the neglect organisations at that time

Define emulation, Define emulation. Given a computer with a particular ...

Define emulation. Given a computer with a particular instruction set, it is possible to explain additional machine instructions and execute them with extra micro routines. Emul

Explain control word, What is control word? A control word is a word wh...

What is control word? A control word is a word whose individual bits show the various control signals.

What are the difference between $display and $strobe, What are the Differen...

What are the Difference between $display and $strobe Difference between $display and $strobe is that $strobe displays parameters at the very end of current simulation time unit

Determine the complete or gate and and gate decoder, Q. Determine the comp...

Q. Determine the complete OR gate and AND gate decoder count for an IC memory with 4096 words of 1 bit each, using the Linear select memory organization and Two dimensional Memory

The alignment of a type ''c'' field in a report, The alignment of a type 'c...

The alignment of a type 'c' field in a report is? ? Left Aligned.

Explain about combinational circuits, Q. Explain about Combinational Circui...

Q. Explain about Combinational Circuits? Combinational Circuit is one of the models for parallel computers. In interconnection networks, different processors correspond with ea

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd