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Q. Illustrate Edge-Triggered flip-flops ?
Edge-triggered flip-flop is used to synchronize state change at the time of a clock pulse transition in place of constant level. A number of edge-triggered flip-flops trigger on rising edge (0 to 1 transition) while others trigger on falling edge (1- to 0 transition). Fig shows clock pulse signal in positive and negative edge-triggered flip-flops.
Effective positive clock transition involves a minimum time known as setup time for that the D input should be maintained at constant value before occurrence of clock transition. In the same way a minimum time known as hold time for which D input should not change after application of positive transition of pulse.
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How to calculate the flowchart
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Implement the following function using a 3 line to 8 line decoder. S (A,B,C) = ∑ m(1,2,4,7) C (A,B,C) = ∑ m ( 3,5,6,7) Ans. Given function S (A,B,C) = m (1,2,4,7)
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