Illustrate about 8259

8259A adds 8 vectored priority encoded interrupts to the microprocessor. We can expand it to 64 interrupt requests by using one master 8259A and 8 slave units. CS and WR should be decoded. Other connections are direct to microprocessor. 

Pins D7 - D0: the bidirectional data connection, IR7 - IR0: Interrupt request, used to request an interrupt and connect to a slave in a system with multiple 8259A.

WR:-Connects to a write strobe signal (upper or lower in a 16 bit system), RD: - Connects to IORC signal, INT: - Connects to INTR pin on the microprocessor from the master and is connected to an IR pin on a slave and INTA: - Connects to INTA pin on the microprocessor.  In a system only master INTA signal is connected A0:- Selects different command words with in the 8259A, CS: - Chip select - enables 8259A for programming and control, SP/EN: - Slave Program (1 for master, 0 for slave)/Enable Buffer (controls data bus transceivers in a large microprocessor based system when in buffered mode) and CAS2-CAS0:- Used as outputs from the master to slaves in cascaded systems. 

                                                            Figure: 8259 Block Diagram