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1. A computer system has a two-level memory cache hierarchy. The L1 cache has a zero hit penalty, a miss penalty of 5 ns and a hit rate of 95 percent. The L2 cache has a miss penalty of 100 ns and a hit rate of 90 percent.
a) How many cycles are lost for each instruction accessing the memory if the CPU clock rate is 2 GHz?
b) We can either increase the hit rate of the topmost cache to 98 percent or increase the hit rate of the second cache to 95 percent. Which improvement would have more impact?
Ans) UDP TCP SPX
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Q. Show Example on Check Sum? Data: 10101001 00111001 Computing Checksum: 10101001 00111001 --------------- Sum 11100010 Receiver Side: 10101
Modulation and DeModulation
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