How many cycles are lost for instruction accessing memory, Computer Networking

Assignment Help:

1.  A computer system has a two-level memory cache hierarchy. The L1 cache has a zero hit penalty, a miss penalty of 5 ns and a hit rate of 95 percent. The L2 cache has a miss penalty of 100 ns and a hit rate of 90 percent.

a)  How many cycles are lost for each instruction accessing the memory if the CPU clock rate is 2 GHz?

b)  We can either increase the hit rate of the topmost cache to 98 percent or increase the hit rate of the second cache to 95 percent.  Which improvement would have more impact?


Related Discussions:- How many cycles are lost for instruction accessing memory

Database management, today, what is the most common or mostly encountered p...

today, what is the most common or mostly encountered problem in terms of database management system?

Explain what is meant by circuit switching, Question 1: (a) Explain wh...

Question 1: (a) Explain what is meant by circuit switching? Give its main shortcoming and explain its relevance in telephone systems. (b) Outline the differences betwee

Determine the computing infrastructure, Determine the computing infrastruct...

Determine the computing infrastructure One solution for the protection of the computing infrastructure is to use digital certificate-based solutions. Users can be given access

Describe ethernet, Describe Ethernet. Ethernet is one of the well-liked...

Describe Ethernet. Ethernet is one of the well-liked networking technologies used these days. It was developed during the early 1970s and is based on specifications as stated i

Video encoder, How to start the video encoding in asp.net with c#

How to start the video encoding in asp.net with c#

The cut-through switching technique work, How does the cut-through switchin...

How does the cut-through switching technique work? Ans) Cut-Through switching copies only the destination address which is the first 6 bytes after the =frame preamble into its b

Factor causing parallel overheads, Factor Causing Parallel Overheads F...

Factor Causing Parallel Overheads Figure clearly explains that the performance metrics are not able to achieve a linear curve in comparison to the enhance in number of process

Thin ethernet wiring, THIN ETHERNET WIRING: Thin Ethernet needs thin c...

THIN ETHERNET WIRING: Thin Ethernet needs thin coax cable that is cost effective and easier to install than thick Ethernet coax. In this case transceiver electronics are creat

Data and block distribution, Data Distribution Data distribution direct...

Data Distribution Data distribution directives tell the compiler how the program data is to be distributed between the memory areas associated with a set of processors. The log

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd