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1. A computer system has a two-level memory cache hierarchy. The L1 cache has a zero hit penalty, a miss penalty of 5 ns and a hit rate of 95 percent. The L2 cache has a miss penalty of 100 ns and a hit rate of 90 percent.
a) How many cycles are lost for each instruction accessing the memory if the CPU clock rate is 2 GHz?
b) We can either increase the hit rate of the topmost cache to 98 percent or increase the hit rate of the second cache to 95 percent. Which improvement would have more impact?
Q. Explain about Virtual Circuit Switching? Virtual Circuit Switching - All packets belong to a message (or) session is preserved. - Single route is selected between s
a) Consider a hypothetical arrangement of ‘self-learning' bridges shown in the figure below. Assuming all are initially empty, give the forwarding tables for each of the bridges B
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what are the main problems of signal propagation?why do radio waves not always follow a straight line?why is reflection both useful and harmful?
Assuming that TCP Reno is used, consider the following diagram illustrating the behaviour of congestion window, and answer the questions below. a) What was the value of sl
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