How can I model a bi-directional net with assignments influencing both source and destination?

Assign statement constitutes a continuous assignment. Changes on the RHS of statement immediately reflect on LHS net. Though, any changes on LHS  don't  get reflected on the RHS. For instance, in following statement, changes to rhs net would update the lhs net however not vice versa.

wire rhs , lhs;

assign lhs=rhs;

System Verilog has introduced a keyword alias that can be used only on nets to have a two-way assignment. For instance, in the subsequent code, any changes to rhs is reflected to the lh s , and vice versa.

module test ();

wire rhs,lhs;

alias lhs=rhs;

In the above instance, any change to either side of net gets reflected on the other side.