How can arithmetic processor be associated to the CPU, Computer Engineering

Assignment Help:

Q. How can this arithmetic processor be associated to the CPU? 

Two mechanisms are used for connecting arithmetic processor to CPU.  

If an arithmetic processor is treated as one of the Input / Output or peripheral units then it's termed as a peripheral processor. CPU transmitsinstructions and data to peripheral processor that performs the needed operations on data and communicates the results back to CPU. A peripheral processor has various registers to communicate with the CPU. These registers can be addressed by CPU as I/O register addresses. Peripheral and CPU processors are generally quite independent and communicate with each other by exchange of information using data transfer instructions. Data transfer instructions should be specific instructions in CPU. This kind of connection is known as loosely coupled.

Instead if the arithmetic processor has a register and instruction set that can be considered an extension of CPU registers and instruction set then it is known as a tightly coupled processor. Here CPU reserves a special subset of code for arithmetic processor. In such a system the instructions meant for arithmetic processor are fetched by CPU and decoded mutually by CPU and arithmetic processor and finally executed by arithmetic processor. So these processors can be considered a logical extension of CPU. These kind of attached arithmetic processors are called as co-processors.  

The concept of co-processor existed in 8086 machine until Intel 486 machines where co-processor was separate. But Pentium at present doesn't have a separate co-processor. In the same way peripheral processors aren't found as arithmetic processors in general. Though many chips are used for specialized I/O architecture.


Related Discussions:- How can arithmetic processor be associated to the CPU

Explain differences between folded and non-folded network, Explain differen...

Explain differences between folded and non-folded network. Folded network: While all the inlets/outlets are connected to the subscriber lines, the logical connection shows as

Where signalling transfer point exist, Signalling transfer point (STP) exis...

Signalling transfer point (STP) exist in (A) Strowger exchange                  (B)  SS7 (C)  Local area network                 (D)  PABX Ans: STP that is stand f

What are the functions of passes used in two-pass assembler, What are the f...

What are the functions of passes used in two-pass assembler? In an assembly language program, two pass translations can handle forward references early. The subsequent task

RISC performance using optimizing compilers, Q. RISC Performance using opti...

Q. RISC Performance using optimizing compilers? Performance using optimizing compilers: As instructions are simple compilers can be developed for efficient code organization a

Explain isdn address structure and its working, Draw the ISDN address struc...

Draw the ISDN address structure and explain how the addressing works? Address Structure: The ISDN address structure is demonstrated in figure. ISDN number part has a maximum

What is nv-ram, Nonvolatile Read Write Memory, also kown as Flash memory. I...

Nonvolatile Read Write Memory, also kown as Flash memory. It is also called as shadow RAM.

Simplify the Boolean expression, The Boolean expression A‾.B + A.B‾ + A.B i...

The Boolean expression A‾.B + A.B‾ + A.B is equivalent to ? Ans. The Boolean expression A‾ .B + A. B‾+ A.B is equivalent to A + B (A‾ .B + A. B‾+ A.B = B( A‾ + A) + A. B‾ =

Explain essential loop in process scheduling, Explain essential loop in Pro...

Explain essential loop in Process Scheduling . The complex part of scheduling is to balance policy enforcement along with resource optimization so as to pick the best job to run

Explain indirect cycle in control unit, Q. Explain Indirect Cycle in contro...

Q. Explain Indirect Cycle in control unit? Once an instruction is fetched the subsequent step is to fetch the operands. The instruction may have indirect and direct addressing

Write miss policy - cache memories, WRITE MISS POLICY:   Write allo...

WRITE MISS POLICY:   Write allocate   fetch on write   fetch entire block, then write word into block   allocate a new block on each writ   allocate block, but

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd