Give the organization of centralized store program control, Computer Engineering

Assignment Help:

Give the organization of centralized store program control (SPC).

Within stored program control systems, a program or set of instructions for the computer that is stored in its memory and the instructions are executed automatically separately by the processor. Carrying out the exchange control functions by programs stored into the memory of a computer led to such name.

Now here are two approaches to organizing stored program control:

1. Centralized: in such type of control, all the control equipment is replaced through a single processor that must be fairly powerful.

2. Distributed: in this type of control, the control functions are shared through several processors inside the exchange itself.

1118_FIG - Typically Centralized SPC Organization.png

FIG - classically Centralized SPC Organization

 

Dual processor architecture may be configured to operate into one of three modes, in centralized SPC:

1. Standby mode: In such mode, one processor is active and another is on standby, both software and hardware wise. The standby processor brought online while active processor fails. A significant requirement of this configuration is the capability of the standby processor to reconstitute the state of the exchange system while this takes over the control.

2. Synchronous duplex mode: In this synchronous duplex mode, hardware coupling is given in between the two processors that execute similar set of instructions and compare the results continuously. The faculty processor is identified and taken out of service instantly, if a mismatch occurs. While the system is operating usually, the two processors have similar data in their memories at all the times and receive all the information from the exchange environment.

3. Load Sharing mode; in this load sharing operation, an incoming call is allocated randomly or into a predetermined order to one of the processors that then handles the call right by completion. Therefore both the processors are active concurrently and share the load and the resources dynamically.


Related Discussions:- Give the organization of centralized store program control

Convert the following into sop form, Convert the following into SOP form ...

Convert the following into SOP form 1. (A+B) (B'+C) (A'+ C) 2. (A'+C) (A'+B'+C') (A+B') 3. (A+C) (AB'+AC) (A'C'+B)

What is the main problem with segmentation, What is the main problem with s...

What is the main problem with segmentation? Problem with segmentation (i) Is with paging, such mapping needs two memory references per logical address that slows down the

Explain how viewstate is being formed, Explain how Viewstate is being forme...

Explain how Viewstate is being formed and how it is keeps on client. The type of ViewState is System.Web.UI.StateBag, which is a dictionary that keeps name/value pairs. View St

How and what data is gathered- simulation, How and what data is gathered- S...

How and what data is gathered- Simulation To make this as realistic as possible, data is required to be gathered over a long period of time. This can be done by sensors near/i

Distinguish between complex type and simple type elements, Problem: (a)...

Problem: (a) (i) Distinguish between Complex Type and Simple Type elements. (ii) List two benefits while using XSDs in XML data modeling. (b) Both XML schema and XSL u

Explain resource request and allocation graph (rrag), Explain Resource requ...

Explain Resource request and allocation graph (RRAG) Deadlocks can be explained by a directed bipartite graph known as a Resource-Request-Allocation graph (RRAG).A graph G = (V

Define dynamic loading, Define dynamic loading. To get better memory-sp...

Define dynamic loading. To get better memory-space utilization dynamic loading is used. With dynamic loading, a routine is not loaded unless it is called. All routines are kept

Direct mapped strategy, Determine the layout of the specified cache for a C...

Determine the layout of the specified cache for a CPU that can address 1G x 32  of memory.  show the layout of the bits per cache location and the total number of locations.  a)

Memory-to-memory architecture:, Memory-to-Memory Architecture : The pipe...

Memory-to-Memory Architecture : The pipelines can access vector operands, intermediate and final results directly in the main memory. This needs the higher memory bandwidth. How

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd