Instruction Pipelines

The stream of instructions in instruction execution cycle may be realized by a pipeline where overlapped executions of various operations are performed. The procedure of executing the instruction includes subsequent main steps:

• Fetch the instruction from main memory
• Decode the instruction
• Fetch the operand
• Execute the decoded instruction

These 4 steps turn out to be the candidates for phase for the pipeline that we know as instruction pipeline (It is displayed in Figure below).

          Figure: Instruction Pipeline

Because in pipelined execution there is overlapped implementation of operations, the 4 phases of the instruction pipeline would work in overlapped manner. Firstly instruction address is fetched from memory to first phase of pipeline. First phase fetches the instruction and gives its output to second phase. Whereas second phase of the pipeline is decoding the instruction, the first phase gets other input as well as fetches the subsequent instruction. When the first instruction has been decoded in second phase then its o/p (output) is fed to the third stage. When third phase is fetching the operand for the first instruction then the second phase gets the second instruction in addition the first phase gets input for other instruction and so on. In this approach the pipeline is implementing the instruction in an overlapped way increasing the speed and throughput of execution.

The scenario of the overlapped operations in instruction pipeline can be explained by the space-time figure. In Figure, firstly we show the space-time figure for non-overlapped execution in a serial environment and then for the overlapped pipelined environment. It's clear from the two figures that in non-overlapped execution results are achieved only after 4 cycles as in overlapped pipelined execution after four cycles we are getting O/P (output) after every cycle. Soon in instruction pipeline the instruction cycle has been decreased to ¼ of the sequential execution.