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A control character is sent at the beginning as well as at the end of every block in the synchronous-transmission in order to
(A) Synchronize the clock of transmitter and receiver.
(B) Supply information required to separate the incoming bits into individual character.
(C) Detect the error in transmission and received system.
(D) Both (A) and (C).
As the data are sent continuously as a block of data at the rate dictated by the clock frequency, so the receiver should be supplied with the similar function about the same bit length in order to interrupt the information.
Will case infer priority register if yes how give an example? Yes case can infer priority register depending on coding style reg r; // Priority encoded mux, always @
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