Q. Explain about Instruction Cycle?

The instruction cycle for this provided machine comprises four cycles. Presume a 2-bit instruction cycle code (ICC). The ICC can represent the state of the processor in terms of cycle. For illustration we can use:

00:  Fetch 

01:  Indirect

10: Execute

11: Interrupt

At the end of each of four cycles ICC is set appropriately. Please note that an indirect cycle is always followed by execute cycle and interrupt cycle is always followed by fetch cycle. For both execute and fetch cycles, the subsequent cycle relies on the state of the system. Let's show an instruction execution employing instruction cycles and timing diagram:

Figure: Timing Diagram for ISZ instruction

Please note that address line decide the location of memory. Read/ write signal controls whether the data is being input or output. For illustration at time T₂ in M₂ read control signal becomes active A₉ - A₀ input comprises MAR that value is kept enabled on address bits and data lines are enabled to accept data from RAM so enabling a typical RAM data output on the data bus.

For reading no data input is applied by CPU however it is put on data bus by memory after the read control signal to memory is activated. Write operation is triggered along with data bus carrying the output value.