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DRAM consists of MOSFET's but the technique is to use the drain source capacitance to hold charge. If charge is present logic '1' is held, no charge logic '0'. As you know capacitors discharge themselves eventually and in order to maintain the data they require topping up. This process of topping up is termed refreshing. This involves supplying row address strobes (RAS) and column address strobes (CAS) to refresh each cell. Shown below are the pining details of a basic DRAM device.
By looking at the internal structure shown below, we can see that the design is more complex since it is required to refresh the cells.
Most modern processors have the required logic built in to refresh DRAM directly namely Pentium, 68060, Power PC etc.
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