Dram, Computer Engineering

Assignment Help:

DRAM consists of MOSFET's but the technique is to use the drain source capacitance to hold charge. If charge is present logic '1' is held, no charge logic '0'. As you know capacitors discharge themselves eventually and in order to maintain the data they require topping up. This process of topping up is termed refreshing. This involves supplying row address strobes (RAS) and column address strobes (CAS) to refresh each cell. Shown below are the pining details of a basic DRAM device.

By looking at the internal structure shown below, we can see that the design is more complex since it is required to refresh the cells.

1092_DRAM.png

Most modern processors have the required logic built in to refresh DRAM directly namely Pentium, 68060, Power PC etc.


Related Discussions:- Dram

Give an example of resource allocation graph & deadlocked, Suppose there ar...

Suppose there are 2 copies of resource A, 3 copies of resource B, and 3 copies of resource C. Suppose further that process 1 holds one unit of resources B and C and is waiting for

Define the heat transfer processes, Heat Transfer Coursework An interna...

Heat Transfer Coursework An internal combustion engine of a passenger car is operating at steady state conditions e.g. constant speed (r.p.m.) and load (torque), so the engine

Adbms, what are the different way of executing pipelines

what are the different way of executing pipelines

Explain characteristics of the artificial neural networks, Question 1: ...

Question 1: Explain in detail the characteristics of the following artificial neural networks. (a) Recurrent Neural Networks. (b) Self-organising Mapping Neural Networks.

Define the operand data types, Operand is that part of an instruction which...

Operand is that part of an instruction which specifies the address of source or result or the data itself on which the processor is to operate. Operand types typically give operand

How many two-input AND and OR gates are required to realize , How many two-...

How many two-input AND and OR gates are required to realize Y=CD+EF+G ? Ans. Y=CD+EF+G No. of two i/p AND gates=2 No. of two i/p OR gates = 2 One OR gate to OR CD and EF

What is scan, What is "Scan"? Scan Insertion and ATPG helps test ASICs ...

What is "Scan"? Scan Insertion and ATPG helps test ASICs (e.g. chips) during manufacture. If you know what JTAG boundary scan is, then Scan is the similar idea except that it i

Define the concept of inheritance, Define the concept of Inheritance I...

Define the concept of Inheritance Inheritance is property of reusing the code within the object oriented development. While modelling, we look at the all the classes, and try

Explain what is the difference among isr & function call, In ISR there is n...

In ISR there is no return value but in function call there is return value

Learning weights in perceptrons, Learning Weights in Perceptrons: Furt...

Learning Weights in Perceptrons: Furthermore details are we will look at the learning method for weights in multi-layer networks next lecture. Thus the following description o

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd