Disadvantages of pipeline:

Pipeline architecture has 2 major disadvantages.  First is its complexity and second is the inability to constantly run the pipeline at full speed, for example. The pipeline stalls.

Let us check why the pipeline cannot run at highest speed. There are phenomena called pipeline hazards which disturb the smooth execution of the pipeline. As a Result delays in the pipeline flow are called bubbles. These pipeline hazards include following

• data hazards arising from data dependencies
• structural hazards from hardware conflicts
• control hazards that come about from instruction  jump, branch and other control flow changes

These two issues can successfully deal with.  But avoiding and detecting the hazards leads  to  a considerable increase in hardware complexity. The control paths that control the gating amongst stages can have more circuit levels than the data paths being controlled. In the year of 1970due to this complexity led Foster to call pipelining "still-controversial" .

The one main idea that is still controversial is "instructions look-ahead" [pipelining]...

Why then the controversy? First, there is a substantial increase in hardware complexity [...]

The second problem [...] when a branch instruction comes along, it is not possible to know in advance of execution which path the program  will take and, if the machine guesses incorrect,  all the partially processed instructions in the pipeline are useless and have to be replaced [...]

In the second edition of Foster's book, published in the year 1976, this passage was gone. Apparent from it, Foster felt that pipelining was no longer controversial.

Doran also alludes to the nature of the problem. Model of the pipelining is "amazingly simple" whilst the implementation is "very difficult" and has many complications.

Because of the multiple instructions that can be in several stages of execution at any given moment in time, managing an interrupt is one of the more difficult tasks. In the IBM 360, this can lead to many instructions executing after the interrupt is signaled, as a result in an imprecise interrupt. An imprecise interrupt may result from an instruction exception and precise address of the instruction because of the exception may not be known! This led Myers to criticize pipelining, that referring to the imprecise interrupt as an "architectural nuisance". He stated that it was not an advance technique in computer architecture but an improvement in implementation that could be treated as a step backward.

In retrospect, most of Myers' book Advances in Computer Architecture dealt with his concepts for improvements in computer architecture that would be termed CISC today. With the advancement of hindsight, we can see that pipelining is present today and that most of the new CPUs are in the RISC class. Actually, Myers is one of the co-architects of Intel's series of 32-bit RISC microprocessors. This processor is fully pipelined.

The harshness arising from imprecise interrupts should be taken as a complexity to be conquer, not as an inherent flaw in pipelining. Doran describes how the B7700 carries the address of the instruction through the pipeline, so that any exception which the instruction may raise can be precisely located and not produced an imprecise interrupt

An instruction pipeline technique is used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

The basic idea is to split the processing of a computer instruction into a series of free steps, with storage at the end of every step. This permit the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time required to perform all steps at once. The term pipeline consider to the fact that each step is carrying data at once (like water), and each step is related to the next (like the links of a pipe.)

The origin of pipelining is thought to be the project. The IBM Stretch Project says the terms, "Fetch, Decode, and Execute" that became ordinary usage.

Most modern CPUs are processed by a clock. The CPU consists internally of logic and memory (flip flops). When the first clock signal arrives, the flip flops take new value and the logic then needed a period of time to decode the new values. Then the second clock pulse arrives and the flip flops again take another new values, and so on. By breaking the logic into smaller pieces and inserting flip flops amongst the pieces of logic, the delay before the logic gives applicable outputs is reduced. In this way the clock period may be reduced. For instance, the RISC pipeline is broken into 5 stages with flip flops at each step between each stage.

• Instruction fetch
• Instruction decodes and registers fetch
• Execute
• Memory access
• Register write back