1. Draw a schematic diagram of a CMOS inverter and explain its operation.

2. Draw schematic diagrams of CMOS NAND and NOR gates, and explain their operation.

3. Explain what is meant by "strong" or "weak" logic levels. Your answer should include a discussion of how n-channel devices "conduct" 1s or 0s.

In each of the following questions, it will be useful to perform a Partition Minimisation procedure to ensure your FSM is minimal.

4. Design a synchronous, MEALY type FSM that has input w and output z. The machine generates an output z = 1 when the previous four values of w were 1001 or 1111, otherwise z = 0. Overlapping input patterns are should be detected. Here's some example output:

w : 010111100110011111

z : 000000100100010011

5. Design a synchronous, MOORE type FSM that also detects the sequences 1001 or 1111. Sketch some example output, and compare your design with the one for question 4.

6. A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles the circuit produces z = 1; otherwise z = 0. Derive a state machine that performs this action. Example inputs and outputs:

w1 : 0110111000110

w2 : 1110101000111

z : 0000100001110

(With reference to the example, is this a Moore or a Mealy machine?)

7. Describe what is meant by a RACE or a HAZARD in an asynchronous circuit. How can they be avoided in designs?

8. A control mechanism for a vending machine accepts 10p and 5p pieces. It dispenses a chocolate bar when 20p is deposited (prices now better reflect the current economic climate); the mechanism does not give change if 25p is deposited. Design an asynchronous FSM that implements the mechanism-use as few states as possible. Use Partition Minimisation and State Merge to ensure your design is as small as possible.

9. How many single stuck-at faults are there in the circuit F = A.B + C? How many double stuck-at faults? How many triple stuck at faults? Use the path sensitisation technique to derive a minimal set of tests for all the single stuck-at faults in the circuit.

10. Draw a schematic diagram of a five-bit array multiplier. Explain its operation. Estimate the worst-case delay through the circuit (in units of full-adder and gate delays).

11. Draw a schematic of a five bit Wallace Tree Multiplier. Estimate the worst-case delay for this circuit.

12. Design a five bit Dadda tree multiplier, and compare its cost and speed with the Wallace Tree Multiplier from question 5.

13. Design a four bit carry-lookahead adder and compare its cost and delay with a four bit ripple carry adder.