Determine the memory access time, Electrical Engineering

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Question:

(a) Explain the types of hazards in a 5 stage pipeline.

(b) Describe the three RAW dependencies in the following instructions.

i: R7←R12+R15
i + 1: R8←R7-R12
i + 2: R15←R8+R7

(d) Consider a main memory and bus such that Tacc = 5, Tbus = 2, and w = 64 bits. For a given application, cache C1 has a hit ratio h1 = 0.88 with a line size L1 = 16 bytes. Cache C2 has a hit ratio h2 = 0.92 with a line size L2 = 32 bytes. The cache access time in both cases is 1 cycle.

Determine the memory access time for the C1 and C2.

(e) Consider the cache (S,m,L) with S = 32KB,m = 1(direct-mapped), and L= 16B. The number of lines is 32 × 1024/16 = 2048. The memory reference can be seen as the triplet (displacement d, tag t, index i).

Determine the values of d, t, i.

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