Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. Describe Program Control Instructions?
These instructions specify conditions for altering the sequence of program execution or we can say in other words that the content of PC (program counter) register. PC points to memory location which holds the subsequent instruction to be executed. The alteration in value of PC as a result of execution of control instruction such as BRANCH or JUMP causes a break in sequential execution of instructions. The most common control instructions are as following:
JUMP and BRANCH may be unconditional or conditional. JUMP is an unconditional branch used to implement simple loops. JNE jump not equal is conditional branch instruction. The conditional branch instructions like BRP X and BRN X causes a branch to memory location X if the result of most recent operation is positive or negative correspondingly. If the condition is true PC is loaded with branch address X and next instruction is taken from X otherwise PC is not changed and the subsequent instruction is taken from location pointed by PC. Figure below displays an unconditional branch instruction and a conditional branch instruction if content of AC is zero.
MBR←0; Assign 0 to MBR register
X←2001; Assume X to be an address location 2001
READ X; Read a value from memory location 2001 into AC
BRZ 1007; Branch to location 1007 if AC is zero (Conditional branch on zero)
ADD MBR; add the content of MBR to AC and store result to AC
TRAS MBR; Transfer the contents of AC to MBR
INC X; Increment X to point to next location
JUMP 1001;Loop back for further processing.
THE NEED OF PARALLEL COMPUTATION With the growth of computer science, computational pace of the processors has also increased many a times. Though, there are definite constr
Explain MIB (Management Information Base) variables. MIB is a set of named items which an SNMP agent knows. To control or monitor a remote computer, a manager should fetch or s
Put an "X" next to any of the following that are RISC CPU characteristics that show diffrence between RISC from CISC a) has limited addressing modes b) used in Motorola 6000 pro
Since the term artificial intelligence was defined in the 1950s, experts have disagreed about the difference between natural and artificial intelligence. Can computers be pro
Explain how a critical section avoids Race condition. To prevent Race Condition, concurrent processes should be synchronized. Data consistency needs that only one process m
Make a class library and describe class 'User'. In User class describe the public, protected and Friend functions. Make a console application andadd a reference to this library and
Disadvantages of Stateful Multi-Layer Inspection A firewall such as the SMLI remains completely transparent to both users and applications. Consequently, SMLI firewall does no
Q. Illustrate Cache DRAM? Cache DRAM (CDRAM) which is developed by Mitsubishi integrates a tiny SRAM cache (16Kb) on a generic DRAM chip. SRAM on the CDRAM can be used in two
Simple instruction formats: RISC uses simple instruction formats. Usually only one or a few instruction formats are used. In these machines instruction length is fixed and alig
Allocation of Bits among Opcode and Operand The trade-off here is between numbers of bits of opcode vs. the addressing capabilities. An interesting development in this regard i
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd