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Describe 74LS139 memory decoder.
The 74LS139 is a dual 2-to-4 line decoder. This contains two separate 2-to-4 line decoders - all with its address, output and enable connections.
The Pin-out of the 74LS139
Q. Balanced wye-connected loads drawing 10 kW at 0.8 power factor lagging and 15 kW at 0.9 power factor leading are connected in parallel and supplied by a 60-Hz, 300-V, three-phas
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How address and data lines are demultiplexed in 8085? AD0-AD7 lines are multiplexed and the lower half of address A0-A7 is available only during T1 of the machine cycle. This
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Q. A common requirement is conversion from one digital code to another.Develop a table of the BCD code and the excess-3 code to be derived from it, for the decimal digits 0 to 9. S
1. Data is to be transmitted using a modem at 9600 bps. Determine the minimum bandwidth of the system with the following modulation methods (a) FSK (b) ASK. Use the excess
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