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The logic circuit shown in the given figure can be minimised to
Ans. The minimised figure of logic diagram is D, the output of the logic circuit is as
Y=(X+Y')'+(X'+(X+Y')')' (X+Y')'=X'Y
By using DE Morgan's here it is one of input of 2nd gate.
F=(A+X')'=A'X=[(X'Y)'.X]=[(X+Y')X]=X+XY'=X(Y')=X
Mr. X's MMPI suggests that he either suppresses anger and hostility or has a naturally low level of anger and hostility (O-H=58, ANG=36, TPA=41, AGGR=36). His responses on the PAS
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Translator for low level programming language were termed as? Ans. Translator for low level programming language is called as Assembler.
If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is ? Ans. The final output of the three T-flip-flops in cascade is 12
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