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The logic circuit shown in the given figure can be minimised to
Ans. The minimised figure of logic diagram is D, the output of the logic circuit is as
Y=(X+Y')'+(X'+(X+Y')')' (X+Y')'=X'Y
By using DE Morgan's here it is one of input of 2nd gate.
F=(A+X')'=A'X=[(X'Y)'.X]=[(X+Y')X]=X+XY'=X(Y')=X
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How branching takes place in Instruction pipeline. Explain with suitable examples
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