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The logic circuit shown in the given figure can be minimised to
Ans. The minimised figure of logic diagram is D, the output of the logic circuit is as
Y=(X+Y')'+(X'+(X+Y')')' (X+Y')'=X'Y
By using DE Morgan's here it is one of input of 2nd gate.
F=(A+X')'=A'X=[(X'Y)'.X]=[(X+Y')X]=X+XY'=X(Y')=X
What and why use fact finding.
Q. A. Which gates are called Universal Gates? Why? B. State and prove any one of the DeMorgen's Laws. Show that these theorems can be extended up to any number of variables.
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