Cache controller

The cache controller is the mind of the cache.  Its responsibilities include:  performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing  the write policy.  Also the cache controller is responsible fordetermining if memory request is cacheable  and if a request is a cache miss or hit. The cache controller detects cache misses and controls receiving andsending the cells. This device also controls interface. The cache controller have a status register, which may be read by the processor. The  bits of the status register can be used to signal to the processor.

The cache controller accepts commands from the processor. Following are the examplesof the commands are

• Reset the Tag Rams
• Set interrupt mask

The cache controller will send a cell to request a cache line when a miss occurs. This cell can also flush an existing dirty line. It  is expecting cell to be returned containing the data, and the CPU is stalled till such a cell is received.