Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Associative Array Processing
Consider that a list of record or a table is stored in the memory and you want to search some information in that list. For example, the list having of three fields as given below:
Name ID Number Age
Sumit 234 23
Ramesh 136 26
Ravi 97 35
Suppose now that we want to search the ID number and age of Ravi. If we use conventional RAM then it is essential to give the exact physical address of entry related to Ravi in the instruction access the entry such as:
READ ROW 3
One more alternative idea is that we seek the whole list using the Name field as an address in the instruction such as:
READ NAME = RAVI
Again with serial access memory this option can be executed easily but it is a very slow process. An associative memory helps at this point and simultaneously looks at all the entries in the list and returns the desired list very fastly.
SIMD array computers have been developed with associative memory. An associative memory is content addressable memory, by which it is says that multiple memory words are accessible in parallel. The parallel accessing feature also gives support parallel compare and parallel search. This capability can be used in following applications such as:
The inherent parallelism element of this memory has great benefits and impact in parallel computer architecture. The associative memory is costly measure to RAM. The array processor built with associative memory is known as Associative array processor. In this part, we describe some of categories of associative array processor. Types of associative processors are relying on the organisation of associative memory. Thus, first we discuss about the associative memory organisation.
Utilization Summary The Utilization Summary shows the status of each processor i.e. how much time (in the form of percentage) have been spent by every processor in busy mode, o
The 68Hc11 is actually a complex micro-controller its contains internally RAM, EEPROM, Parallel IO and serial ports, hardware timers and a 8 channel ADC. The internal structure is
Explain Language Processor Development Tools (LPDTs) through schematic diagram. LPDT that is Language processor development tools focuses upon generation of the analysis phase
Can we specify file transfer in a Web page? Explain with the help of suitable example. Yes, file transfer can be given in a web page. The first field within a URL gives a proto
Illustrate the basic structure of the von Neumann machine The following figure shows basic structure of the von Neumann machine. A von Neumann machine has only a single path be
Indirect addressing A memory location is given that holds another memory location. This second memory location holds the real data. This mechanism solves problems caused by rea
Q. What is Multiple Interrupt Lines? Multiple Interrupt Lines: Simplest solution to problems above is to provide multiple interrupt lines that will result in immediate recognit
Processing elements (PEs) : Every processing element consists of ALU, local memory and its registers for storage of distributed data. This PEs has been interconnected via an inte
Software Engineering is a layered technology. Explain
Program Level This is normally the liability of OS (operating system) that runs processes simultaneously. Different programs are generally independent of each other. So paralle
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd