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i) The width of the sorting + merging circuit is equivalent to maximum number of devices needed in a phase is O(n/2). As in the above diagram maximum number of devices for a given phase is 4 that is 8/2 or n/2.
ii) The circuit comprises two sorting circuits for sorting sequences of length n/2 and afterwards one merging circuit for merging of two sorted sub sequences (see phase 4th in above figure). Let functions Tm and Ts signify the time complexity of merging and sorting in terms of its depth.
The Ts can be calculated as follows:
Ts (n) =Ts (n/2) + Tm (n/2)
Ts (n) =Ts (n/2) + log (n/2),
Therefore, Ts (n) is equal to O (log2 n).
Figure: Sorting + Merging Circuit
Relocation bits used by relocating loader are specified by? Ans. Relocation bits utilized by relocating loader are identified by Assembler or Translator.
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