Write vhdl code to implement a 3-input 3-bit multiplexer

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Reference no: EM13263301

Write VHDL code to implement a 3-input 3-bit multiplexer. The select inputs are S0-S1, the data inputs are A2-A0, B2-B0, C2-C0, and the data outputs are Y2-Y0. The outputs Y2-Y0 should be equal to A2-A0,B2-B0,C2-C0 for the select-input combinations 00,01,10, respectively and should be zero when the select inputs are 11.

Reference no: EM13263301

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