Reference no: EM131090127

The overall objective of this lab is to build an LCD graphics display like the one described in Section 10.5.1. This is a complicated design that requires organization and testing. The first step is to choose digital logic devices fast enough for both the computer interface and the LCD timing. At 2 MHz 74HC logic will suffice, but at 25 MHz careful design and LCD layout will be required. One option for interfacing the system to a microcontroller running in single-chip mode is to interface a 19-bit shift register (15 address lines and 4 data lines) to the SPI. To write data into the back buffer, the software outputs three bytes to the SPI (address and data) then pulses it into the back buffer with a simple digital output line. Another option is to design a single buffered solution. In this system the counters and 19-bit shift registers have tristate outputs. To write to the buffer, the software activates the outputs of the shift registers, disables the outputs of the Row and Column counters, and stops the display clock. After the memory write cycle is complete, the software disables the outputs of the shift registers, enables the outputs of the Row and Column counters, and restarts the display clock. The second part of the lab is the design of a low-level graphics device driver, which allows for drawing lines, drawing dots, displaying text, and erasing portions of the screen