Write a vhdl procedure that will add two bit-vectors

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Reference no: EM131367715

Write a VHDL procedure that will add two bit-vectors that represent signed binary numbers. Negative numbers are represented in 2's complement. If the vectors are of different lengths, the shorter one should be sign-extended during the addition. Make no assumptions about the range for either vector. The procedure call should be of the form Add2(A, B, Sum, V), where V = 1 if the addition produces a 2's complement overflow.

Reference no: EM131367715

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