Write a vhdl model for the flip-flop

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Reference no: EM131367626

A clocked T flip-flop has propagation delays from the rising edge of CLK to the changes in Q and Q' as follows: If Q (or Q') changes to 1, t _plh = 8 ns, and if Q (or Q') changes to 0, t _phl = 10 ns. The minimum clock pulse width is t _ck = 15 ns, the setup time for the T input is t su = 4 ns, and the hold time is t _h = 2 ns. Write a VHDL model for the flip-flop that includes the propagation delay and that reports if any timing specification is violated. Write the model using generic parameters with default values.

Reference no: EM131367626

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