Write a vhdl description of the digital system

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Reference no: EM131368048

For the given SM chart:

2460_37835e7a-0aba-4fbe-8ecb-f15b82b654ff.png

(a) Complete the following timing diagram (assume that X1 = 1, X2 = 0, X3 = 0, X5 = 1, and X4 is as shown). Flip-flops change state on falling edge of clock.

(b) Using the given one-hot state assignment, derive the minimum next state and output equations by inspection of the SM chart.

1558_b295e9a1-e83f-4d82-93bb-06be6cb7bd95.png

(c) Write a VHDL description of the digital system.

Reference no: EM131368048

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