Why the mealy synchronous sequential circuit has one input

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Reference no: EM13263480

A "Mealy" synchronous sequential circuit has one input X and one output Z. An output Z = 1 occurs every time the total number of 1's received is "divisible by 3" AND the total number of 0's received is an even number greater than zero. Construct a state transition diagram and make sure that the final number of states can't be reduced. Do NOT design the circuit. Note a "0" is divisible by 3.

Reference no: EM13263480

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