You are designing a Prime Number Detector using VHDL. Your circuit will be implemented with combinational logic using a concurrent signal assignment and logical operators. The detector will take in numbers from 1510 to 010 encoded in binary labeled [N3:N0] with N3 being the most significant bit. The output will be asserted when the decimal value of the input is a prime number (i.e., 2,3,5,7,11,13). The output is de-asserted otherwise.

4 Inverters are given to produce the inverted values of each input as follows:

N3n <= not N3;

N2n <= not N2;

N1n <= not N1;

N0n <= not N0;

Which is the correct syntax for the concurrent signal assignment of the complete sum for the detector?

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