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Consider a static CMOS inverter that can drive a capacitive load of 0.05pF.
Assume the following parameters:
VDD = 3 volts,
Vtn = - Vtp = 0.7 volts,
K'n= 120 A/volts2
K'p= 60 A/volts2
The length of the n-channel and the p-channel are Ln = Lp = 0.8 m.
Assume that the p-channel is twice as wide as the n-channel.
a) It is required that the propagation delay be limited to 60 psec. Find the required device widths
b) Find the High and Low noise margins, i.e. NMH and NML.
c) What is the peak current drawn from VDD during switching of the inverter?
What is the average current drawn from the power supply?
d) What is the dynamic power dissipation that results when the inverter is switched at a frequency of 2 MHz?
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the project manager on a development project working on a new line of laptop computers. The project has been broken down into the following modules: Power supply, Processor and motherboard with RAM, I/O circuit board
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write an 8051 program that would generate a 200khz, 50% duty cycle, square wave at P1.0.Use Timer 0 for the delay. Ignore the overheads cycles due to the instructions in the loop. Assume 12 MHz clock. All data must be hex.
(a) If the excitation volatge Eo is equal to the terminal voltage ( 4kv ), what is the maximum real power which the motor can deliver without losing synchronism (b) What is the rotor pole shift in electrical degrees
Explain why the short-circuit method for determining the Thevenin resistance of a circuit cannot be applied if the circuit does not contain any independent current or voltage sources.
An 8-bit A/D converter has Vref- = 2 V and Vref+ = 5 V. The analog input signal vin has a frequency range of 300 Hz to 3.4 kHz. a) If vin = 7 V, what is the binary value on the A/D output pins b) If vin = 1 V, what is the binary value on the A/D outp..
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