Using min num of external gates draw circuit logic diagram

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Reference no: EM13263433

Using synchronous Finite State Machine, design a sequential circuit that asserts a high output (Z) for exactly three clock pulses when an input button (B) is pushed (i.e. asserted). The circuit should stay idle with low output, when the button (B) is not pushed (not asserted).Draw the state diagram, and circuit logic diagram. Use minimal number of external gates. [Hint: Use positive edge triggered D flip-flops]

Reference no: EM13263433

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