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1) The SOP expression for c8 in a carry-lookahead adder is
c8 = g7 + p7g6 + p7p6g5 + p7p6p5g4 + p7p6p5p4g3 + p7p6p5p4p3g2++ p7p6p5p4p3p2g1 + p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0
Show how to implement this expression if only gates with at most 4 inputs can be used. Rewrite the expression for c8 using parentheses to show the associated grouping of inputs. Sketch and label the corresponding circuit and determine its cost. The ?rst priority for optimization is to keep the longest delay from any of the inputs to the c8 output as short as possible. The second priority is to minimize the cost of the circuit. Compare the longest delay from input to output and the cost of your circuit to the cost and delay of a direct SOP implementation (without gate input constraints) for c8.
Attachment:- digital logic.zip
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