Provide separate instruction and data memories

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Modify the design in Figure 7.8 to provide separate instruction and data memories for the 8051: a 64K × 8-bit ROM for the instruction memory and a 64K × 8-bit asynchronous SRAM for the data memory. The ROM has the same control signals as the SRAM except for the

568_4266468c-5815-400e-9d36-1ccf9f850e9f.pngsignal.

Reference no: EM131201192

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