How many dffs are needed to build

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Synchronous Pulse Stretcher Solve exercise 9.12 using SystemVerilog instead of VHDL.

Exercise 12 in Chapter 9

Synchronous Pulse Stretcher This exercise concerns the synchronous pulse stretcher introduced in figure 8.28a.

(a) How many DFFs are needed to build it for T = 64 clock cycles and sequential encoding?

(b) Implement it using VHDL. Check whether the number of DFFs inferred by the compiler matches your estimate.

(c) Recompile it for T = 5 and simulate it with the same stimuli of figure 8.28b, checking if the same waveforms result.

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Reference no: EM131186195

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