How many and gates are required for decoding an address

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Reference no: EM13291417

A 64K x 16 RAM chip uses coincident decoding by splitting theinternal decoder into row select and column select. (a) Assumingthat the RAM cell array is square, what is the size of eachdecoder, and how many AND gates are required for decoding anaddress? (b) Determine the row and column selection lines that areenabled when the input address is the binary equivalent of(32000)₁₀

Reference no: EM13291417

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