How does given limit the application of the sample hold

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Reference no: EM131392487

A sample-and-hold circuit like the one shown in Figure has C = 0.47 µF, and the ON resistance of the FET is 75Ω.

For what signal frequency is the sampling capacitor voltage down 3 dB from the signal voltage? How does this limit the application of the sample hold?

1790_Figure 07.jpg

Reference no: EM131392487

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