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A balanced wye-connected load of (4 + j3) Ω is connected across a three-phase source of 173 V (line-to-line).
a. Find the transmission line current.
b. Find the power factor, the complex power, the real power, and the reactive power of the load.
c.With Vab as the reference, sketch the phasor diagram that shows all voltages and currents.
Design a filter for a biomedical instrument to eliminate DC (f = 0), 500 Hz tone, and its corresponding harmonics. The system sampling rate is 2,000 Hz. Place all the required poles at the origin to obtain a FIR filter.
a 741C is an op amp with Av= 100000 and a minimum CMRRdB= 70dB. what is the common- mode voltage gain. if a desired and common- model signal each has a value of 5 uV. what is the output voltage.
Write a VHDL module for a 4-bit adder, with a carry-in and carry-out, using an overloaded addition operator and std_logic_vector inputs and outputs.
The sending-end voltage, current, and power factor of the line described in Example 6.3 are found to be 260 kV (line to line), 300 A, and 0.9 lagging, respectively. Find the corresponding receiving-en d voltage, current, and power factor.
Suppose a pure Si crystal has 5 × 1028 atoms m-3. It is doped by 1 ppm concentration of pentavalent As. Calculate the number of electrons and holes. Given that ni =1.5 × 1016 m-3.?
To become familiar with computations involving phasors and the complex representation of sinusoidal ac powers, including the effect of power factor (PF) improvement on both the line current and voltage sources.
Dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns. memory cycle requires 250 ns.
Calculate IB and IE for 0
an electrical conductor designed to carry large currents has a circular cross section 2.50 mm in diameter and is 14.0 m
A sinusoidal voltage has maximum amplitude of 90 V. The voltage passes through one complete cycle in 64 ms. What is the frequency of the voltage in hertz
A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder into a four stage pipeline adder proceed as following.
Consider the two-path example d = 2 km and the receiver at 1.5 km from the transmitter moving at velocity 60 km/h away from the transmitter. The carrier frequency is 900 MHz. Plot in MATLAB the magnitudes of the taps of the discrete-time baseb..
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