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It is desired to determine the effect of package style on the number of circuits (logic gates) that can be fabricated onto an IC chip to which the package is assembled. Using Rent's rule with C = 4.5 and m = 0.5, compute the estimated number of devices (logic gates) that could be placed on the chip in the following cases:
(a) a DIP with 16 I/O pins on a side-a total of 32 pins;
(b) a square chip carrier with 16 pins on a side-a total of 64 I/O pins; and
(c) a pin grid array with 16 by 16 pins-a total of 256 pins.
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Nan crystalline materials have grain sizes ranging from 0.01 to 0.1 microns. If the contribution of grain boundary strengthening in an alloy with grains of 0.1 microns is 20 MPa, what would you expect it to be if the grain size were reduced to 0.01 m..
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